Reduction of power consumption of integrated circuits is of increasing importance when more and more electronic devices are constrained by finite power supplies. There are two types of power consumption in integrated circuits: static and dynamic. Static power is consumed at all times when devices in an integrated circuit are energized, and the static power consumption may change depending on the operating mode of the integrated circuit. The static power consumption usually depends on the semiconductor technology used to synthesize the integrated circuit. On the other hand, dynamic power is consumed only when the state of a device changes. For example, when a node in an integrated circuit changes from a low voltage to a high voltage, the power consumed during that change is classified as dynamic power which is often affected by how the designed circuit functions. Therefore, the dynamic power consumption and the related state change are usually investigated for power reduction during an early stage of a circuit-design process.
Latches are one of the basic building blocks of integrated circuits and often determine circuit speed and power consumption. A latch often includes a circuit that has two stable states and can be used to store state information. A latch may be set to be transparent. That is, the latch forwards signals from its input to its output with no modification, when a control input (e.g., a clock signal) is at a certain logic level. When several transparent latches follow each other, using a same control input, signals can propagate through all of them in a short time period. A transparent latch becomes non-transparent or opaque when a control input (e.g., a clock signal) is at the opposite logic level. An opaque latch holds its output value steady regardless of signals that arrive at its input.
For example, a p-latch becomes transparent in response to a clock signal being at logic high. That is, the p-latch passes a data signal from the input to the output when the clock signal is at logic high. An n-latch becomes transparent in response to a clock signal being at logic low. Large scale integrated circuits may be divided into discrete stages by placing p-latches and/or n-latches to regulate the data flow.